DocumentCode :
1983042
Title :
Unifying memory and processor wrapper architecture in multiprocessor SoC design
Author :
Gharsalli, Férid ; Lyonnard, Damien ; Meftali, Samy ; Rousseau, Frédéric ; Jerraya, Ahmed A.
Author_Institution :
Lab. TIMA, Grenoble, France
fYear :
2002
fDate :
2-4 Oct. 2002
Firstpage :
26
Lastpage :
31
Abstract :
In this paper, we present a new methodology for application specific multiprocessor system-on-chip design. this approach facilitates the integration of existing components with the concept of wrapper. Wrappers allow automatic adaptation of physical interfaces to a communication network. We also give a generic architecture to produce these wrappers, either for processors or for other specific components such as memory IP. This approach has successfully been applied on a low-level image processing application.
Keywords :
memory architecture; multiprocessing systems; parallel architectures; system-on-chip; System-on-Chip; application specific; memory wrapper generation; multiprocessor system-on-chip design; system architecture; wrapper; Clocks; Communication networks; Computer architecture; Hardware; Libraries; Memory architecture; Network synthesis; Protocols; Transducers; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
System Synthesis, 2002. 15th International Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
1-58113-576-9
Type :
conf
Filename :
1227147
Link To Document :
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