A novel BST storage capacitor node technology using platinum electrodes for Gbit DRAMs

Author

Khamankar, R.B. ; Kressley, M.A. ; Visokay, M.R. ; Moise, T. ; Xing, G. ; Nemoto, S. ; Okumo, Y. ; Fang, S.J. ; Wilson, A.M. ; Gaynor, J.F. ; Hurd, T.Q. ; Crenshaw, D.L. ; Summerfelt, S. ; Colombo, L.

Author_Institution

Texas Instrum. Inc., Dallas, TX, USA

fYear

1997

fDate

10-10 Dec. 1997

Firstpage

245

Lastpage

248

Abstract

A new stack capacitor structure using barium strontium titanate (BST) has been developed for Gbit scale DRAMs. The feasibility of fabrication of this structure using Pt as the electrode material is demonstrated through the use of novel processes. An appropriately placed oxidation resistant barrier and adhesion layers enhance the thermal and physical stability of the bottom electrode structure. Electrical results, including AC electrical stress reliability measurements, for 3-D storage nodes with side-wall contribution are presented. Fence-free etching of Pt for bottom electrode formation is shown using a new hardmask based process. Successful back-end integration (ILD and metallization) of BST capacitors is also demonstrated.

Keywords

DRAM chips; barium compounds; capacitors; dielectric thin films; etching; integrated circuit reliability; masks; sputtered coatings; strontium compounds; AC electrical stress reliability measurements; BaSrTiO/sub 3/; Gbit DRAMs; adhesion layers; back-end integration; bottom electrode structure; fence-free etching; hardmask based process; oxidation resistant barrier; physical stability; side-wall contribution; storage capacitor node technology; Barium; Binary search trees; Capacitors; Electrodes; Fabrication; Oxidation; Platinum; Resistance; Strontium; Titanium compounds;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-4100-7

Type

conf

DOI

10.1109/IEDM.1997.650372

Filename

650372