Modeling assembly instruction timing in superscalar architectures

Author

Beltrame, G. ; Brandolese, C. ; Fornaciari, W. ; Salice, F. ; Sciuto, D. ; Trianni, V.

Author_Institution

CEFRIEL Res. Centre, Milan, Italy

fYear

2002

fDate

2-4 Oct. 2002

Firstpage

132

Lastpage

137

Abstract

This paper proposes an original model of the execution time of assembly instructions in superscalar architectures. The approach is based on a rigorous mathematical model and provides a methodology and a toolset to perform data analysis and model tuning. The methodology also provides a framework for building new trace simulators for generic architectures. The results obtained show a good accuracy paired with a satisfactory computational efficiency.

Keywords

instruction sets; parallel architectures; performance evaluation; assembly instruction timing modelling; assembly instructions; data analysis; execution time; generic architectures; model tuning; rigorous mathematical model; superscalar architectures; trace simulators; Assembly; Buildings; Computational modeling; Computer architecture; Hardware; Large Hadron Collider; Ovens; Performance analysis; Software tools; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

System Synthesis, 2002. 15th International Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

1-58113-576-9

Type

conf

Filename

1227165

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1983439