Hardware Implementation of an Iterative Sampling Rate Converter for Wireless Communication

This paper presents a new technique for fractional sample rate conversion based on an iterative Sinc (ISRC) method. The proposed algorithm was evaluated against the Farrow resampler, and performance simulation targeting different signal-to- noise ratios show the ISRC qualifies for application in reconfigurable terminals. The architecture was implemented in 65 nm CMOS technology, and synthesis results show that the ISRC requires at least 23% less silicon area, compared to a Farrow filter with similar performance. The generic nature of the architecture enables further area reduction by time-multiplexing.