Automated Synthesis of FSMD-Based Accelerators for Hardware Compilation

Author

Kavvadias, Nikolaos ; Masselos, Kostas

Author_Institution

Ajax Compilers, Athens, Greece

fYear

2012

fDate

9-11 July 2012

Firstpage

157

Lastpage

160

Abstract

In this work we extend the FSMD (Finite-State Machine with Datapath) model to encompass synchronous memory accesses, intermodule communication and hardware-optimizing transformations. A lightweight typed assembly language, N-Address Code (NAC), is used as a designer-friendly representation of FSMDs, simplifying the adaptation of hardware synthesis with existing frontends.The quality (computation time, chip area) of the generated FSMDs has been evaluated on modern FPGAs. Our approach overcomes the C code limitations of four HLS tools while maintaining a good speed/area balance.

Keywords

field programmable gate arrays; finite state machines; hardware description languages; high level synthesis; C code limitation; FPGA; FSMD-based accelerator; HLS tool; N-address code; NAC; automated synthesis; finite-state machine with datapath; hardware compilation; hardware-optimizing transformation; intermodule communication; lightweight typed assembly language; speed-area balance; synchronous memory access; Benchmark testing; Hardware; Optimization; Registers; Sparks; Table lookup; FPGA; FSMD; Field-Programmable Gate Array; Finite-State Machine with Datapath; HLS; high-level synthesis;

fLanguage

English

Publisher

ieee

Conference_Titel

Application-Specific Systems, Architectures and Processors (ASAP), 2012 IEEE 23rd International Conference on

Conference_Location

Delft

ISSN

2160-0511

Print_ISBN

978-1-4673-2243-0

Electronic_ISBN

2160-0511

Type

conf

DOI

10.1109/ASAP.2012.29

Filename

6341467