Title :
Long Residue Checking for Adders
Author :
Sullivan, Michael B. ; Swartzlander, Earl E., Jr.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Texas at Austin, Austin, TX, USA
Abstract :
As system sizes grow and devices become more sensitive to faults, adder protection may be necessary to achieve system error-rate bounds. This study investigates a novel fault detection scheme for fast adders, long residue checking (LRC), which has substantive advantages over all previous separable approaches. Long residues are found to provide a ~10% reduction in complexity and ~25% reduction in power relative to the next most efficient error detector, while remaining modular and easy to implement.
Keywords :
adders; circuit complexity; error detection codes; fault diagnosis; logic testing; LRC; adder protection; complexity reduction; error detector; fault detection scheme; long residue checking; system error-rate bound; Adders; Complexity theory; Computers; Delay; Libraries; Pipelines; Standards; Adder; lazy checker; long residue checker (LRC); residue checking; self-testing and self-checking circuitry; standard cell synthesis;
Conference_Titel :
Application-Specific Systems, Architectures and Processors (ASAP), 2012 IEEE 23rd International Conference on
Conference_Location :
Delft
Print_ISBN :
978-1-4673-2243-0
Electronic_ISBN :
2160-0511
DOI :
10.1109/ASAP.2012.31
