Title :
Integration of (Ba,Sr)TiO/sub 3/ capacitor with platinum electrodes having SiO/sub 2/ spacer
Author :
Byoung Taek Lee ; Ki Hoon Lee ; Cheol Seong Hwang ; Wan Don Kim ; Hideki Horii ; Hyoun-Woo Kim ; Hag-Ju Cho ; Chang Seek Kang ; Ju Hyuck Chung ; Sang In Lee ; Moon Yong Lee
Author_Institution :
Semicond. R&D Center, Samsung Electron. Co., South Korea
Abstract :
An integrated BST capacitor with Pt electrodes and TiSiN diffusion barrier, covered by SiO/sub 2/ spacers, is fabricated. Excellent diffusion barrier and oxidation resistant properties of TiSiN, further protected from being oxidized by the SiO/sub 2/ spacer, make post annealing up to 650/spl deg/C possible. The 0.3/spl times/0.8 /spl mu/m/sup 2/ sized capacitor having 0.2 /spl mu/m height with 256 M density shows 72 fF/cell of capacitance and 1.0 fA/cell@+1.0 V of leakage current density after the post annealing at 650/spl deg/C. The capacitance corresponds to a value of 25 fF/cell of a DRAM with 0.30 /spl mu/m-pitch, which is expected to be the cell size of 1 giga-bit density DRAM.
Keywords :
DRAM chips; ULSI; annealing; barium compounds; capacitors; dielectric thin films; diffusion barriers; leakage currents; strontium compounds; 0.2 micron; 0.3 micron; 256 Mbit to 1 Gbit; 650 degC; 72 fF; DRAM; Pt-BaSrTiO/sub 3/; ULSI; capacitors; dielectric thin films; diffusion barrier; giga-bit density circuits; leakage current density; oxidation resistant properties; post annealing; Annealing; Binary search trees; Capacitance; Capacitors; Electrodes; Leakage current; Plasma temperature; Platinum; Random access memory; Sputtering;
Conference_Titel :
Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-4100-7
DOI :
10.1109/IEDM.1997.650374
