Title :
VLSI implementation of the arithmetic Fourier transform
Author :
Fisher, G. ; Tufts, D.W. ; Unnikrishnan, R.
Author_Institution :
Dept. of Electr. Eng., Rhode Island Univ., Kingston, RI, USA
Abstract :
The arithmetic Fourier transform (AFT) is a promising algorithm for accurate high-speed Fourier analysis. It is based on the number-theoretic method of Mobius inversion. Its computations proceed in parallel, and, except for a small number of scalings in one stage of the conjunction, only multiplications by 0, -1, and +1 are required. The implementation of an AFT channel by switched-capacitor (SC) techniques is presented. The circuit consists of one op amp, two capacitors (one for the sample and hold (S/H) stage, and one for the data accumulation), and a couple of CMOS transmission gates which serve as switches. If necessary, the accumulated data, corresponding to the intermediate sums in the AFT algorithm, can be converted to digital signals for further processing. This analog sampled data solution eliminates the requirement for a fast A/D conversion at the input
Keywords :
CMOS integrated circuits; VLSI; digital arithmetic; fast Fourier transforms; switched capacitor networks; CMOS transmission gates; Mobius inversion; SC networks; arithmetic Fourier transform; data accumulation; digital signals; high-speed Fourier analysis; intermediate sums; number-theoretic method; Algorithm design and analysis; Arithmetic; Concurrent computing; Coupling circuits; Fourier transforms; Operational amplifiers; Switched capacitor circuits; Switches; Switching circuits; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1989., Proceedings of the 32nd Midwest Symposium on
Conference_Location :
Champaign, IL
DOI :
10.1109/MWSCAS.1989.101976
