A high-performance architecture for irregular LDPC decoding algorithm using input-multiplexing method

A new high-performance architecture for decoding the irregular Low-Density Parity-Check (LDPC) codes with respect to the iterative message-passing decoding algorithm is explored. The proposed method is based on reducing the logic delays in the iterative processing of the bit nodes and check nodes leading to the increment of maximum possible frequency. The simulations show the efficiency of the proposed method in low/high-complexity graph matrices, though it is more effective in high-complexity ones. About 28% reduction of the combinational delay in the bit/check processors is explored without much impacting the area consumption.