An ultra-low-power SAR ADC with an area-efficient DAC architecture

An ultra-low-power area-efficient 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) is presented. To achieve ultra-low-power performance a DAC architecture is proposed that employs two rail-to-rail low-power unity-gain buffers and only 4 minimum-size capacitors instead of the conventional binary-weighted capacitor array. Thereby, power consumption and area are drastically reduced by virtue of lower switching activity and smaller size capacitor array. The proposed 8-bit SAR ADC is designed and simulated in a 0.13μm CMOS process. Simulation results show that for a 2.4 kHz (12.4 kHz) input signal while sampling at 25 kHz, the ADC achieves an ENOB of 7.9 (7.8), consumes 290 nW (350 nW) form a 0.8 V analog supply and a 0.6 V digital supply, and achieves a FoM of 48 fj/conversion-step (62 fj/conversion-step).