DocumentCode :
1984757
Title :
Optimizing C compiler for the TRON architecture
Author :
Matsunami, Kunihiko ; Yamana, Tomoko ; Ito, Haruyasu
Author_Institution :
Fujitsu Devices Inc., Kawasaki, Japan
fYear :
1992
fDate :
2-4 Dec 1992
Firstpage :
77
Lastpage :
87
Abstract :
A discussion is given on the development and effects of an optimizing C compiler for the GMICRO F32 series of 32 bit microprocessors which are available for the TRON (the real time operating system nucleus) architecture. Compiler optimizations for the TRON architecture, or the CISC (complex instruction set computer) architecture with its distinct features, were achieved through a clarification of the conflict (trade-off) between the increased execution rate and the reduced object size to produce an optimizing C compiler. In particular, the application of the `1:2 rule´ to the execution rate and the object size achieved the compiler optimization for this CISC architecture. That this optimizing C compiler will accomplish the objective of applying many types of application programs written in C language to the TRON architecture
Keywords :
C language; instruction sets; microprocessor chips; program compilers; standards; 32 bit; CISC; GMICRO F32 series; TRON architecture; complex instruction set computer; optimizing C compiler; the real time operating system nucleus; ANSI standards; Application software; Computer aided instruction; Computer architecture; Indium tin oxide; Microprocessors; Operating systems; Optimizing compilers; Program processors; Real time systems;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
TRON Project Symposium, 1992. Proceedings., Ninth
Conference_Location :
Tokyo
ISSN :
1063-6749
Print_ISBN :
0-8186-2990-8
Type :
conf
DOI :
10.1109/TRON.1992.313265
Filename :
313265
Link To Document :
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