An optimizing C compiler for the GMICRO/500 microprocessor

Author

Kashiwagi, Yugo ; Tawara, Yasuhiro ; Chaki, H. ; Yamada, Kouji ; Kainaga, Masahiro ; Isobe, Tatsuo

Author_Institution

Semicond. Design & Dev. Center, Hitachi Ltd., Tokyo, Japan

fYear

1992

fDate

2-4 Dec 1992

Firstpage

63

Lastpage

69

Abstract

The GMICRO/500 is a superscalar microprocessor based on the TRON specification. An optimizing C compiler for the microprocessor is under development. The compiler implements both hardware-independent optimizations and GMICRO/500-specific optimizations with a performance target of 100 MIPS at 50 MHz. The hardware-independent optimizations gave a good basis for the effective improvement of hardware/software performance. On the other hand, GMICRO-specific optimizations was a challenging problem because of the complexity of the superscalar CISC architecture. The authors describe these optimization techniques with emphasis on the implementation strategy of the GMICRO/500-specific superscalar optimization

Keywords

C language; parallel architectures; pipeline processing; program compilers; GMICRO/500-specific optimizations; GMICRO/500-specific superscalar optimization; TRON specification; hardware-independent optimizations; implementation strategy; optimization techniques; optimizing C compiler; Clocks; Computer architecture; Design optimization; Hardware; Laboratories; Microprocessors; Optimizing compilers; Performance analysis; Program processors; Software engineering;

fLanguage

English

Publisher

ieee

Conference_Titel

TRON Project Symposium, 1992. Proceedings., Ninth

Conference_Location

Tokyo

ISSN

1063-6749

Print_ISBN

0-8186-2990-8

Type

conf

DOI

10.1109/TRON.1992.313267

Filename

313267