DocumentCode
1984901
Title
Memory design to improve testability
Author
Noore, Afzel
Author_Institution
Dept. of Electr. & Comput. Eng., West Virginia Univ., WV, USA
fYear
1989
fDate
14-16 Aug 1989
Firstpage
825
Abstract
A design-for-testability technique for enhancing the testability of read-write memories is proposed. Parallel testing reduces the test complexity by an order of magnitude. The design does not require additional pins. When the column decoder is inactive in the test mode, control inputs can be activated using the existing pins to exercise various test algorithms. The design is versatile, and several well-known test algorithms can be used
Keywords
DRAM chips; integrated circuit testing; logic testing; column decoder; design-for-testability technique; parallel testing; read-write memories; test algorithms; test complexity; Algorithm design and analysis; Costs; Decoding; Design engineering; Design for testability; Read-write memory; Shift registers; Strontium; Testing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1989., Proceedings of the 32nd Midwest Symposium on
Conference_Location
Champaign, IL
Type
conf
DOI
10.1109/MWSCAS.1989.101982
Filename
101982
Link To Document