Title :
A high-speed FIR adaptive filter architecture using a modified delayed LMS algorithm
Author :
Meher, Pramod K. ; Maheshwari, Megha
Author_Institution :
Dept. of Embedded Syst., Inst. for Infocomm Res., Singapore, Singapore
Abstract :
In this paper, we present a modified delayed least means square (DLMS) adaptive algorithm to achieve lower adaptation-delay. Besides, we have proposed an efficient pipelined architecture for the implementation of this adaptive filter. We have shown that the proposed DLMS adaptive filter can be implemented by a pipelined inner-product computation unit for calculation of feedback error, and a pipelined weight-update unit consisting of N parallel multiply accumulators, for filter order N. From the synthesis results we find that the existing direct-form structure of [8] involves nearly 50% more area-delay product (ADP) and nearly 74% more energy per sample (EPS) than the proposed one, in average, for filter orders N = 8,16 and 32. The best of the existing systolic structures [7], similarly, involves nearly 43% more ADP and nearly 35% higher EPS than the proposed one for the same filter orders.
Keywords :
FIR filters; adaptive filters; least mean squares methods; pipeline arithmetic; secondary cells; N parallel multiply accumulators; adaptation-delay; feedback error; high-speed FIR adaptive filter; least means square; modified delayed LMS algorithm; pipelined architecture; pipelined inner-product computation unit; pipelined weight-update unit; systolic structures; Computer architecture; Convergence; Delay; Finite impulse response filter; Least squares approximation; Pipeline processing; Very large scale integration;
Conference_Titel :
Circuits and Systems (ISCAS), 2011 IEEE International Symposium on
Conference_Location :
Rio de Janeiro
Print_ISBN :
978-1-4244-9473-6
Electronic_ISBN :
0271-4302
DOI :
10.1109/ISCAS.2011.5937516