DocumentCode
1985048
Title
On CMOS bridge fault modeling and test pattern evaluation
Author
chennian Di ; Jess, J.A.G.
Author_Institution
Eindhoven Univ. of Technol., Netherlands
fYear
1993
fDate
6-8 April 1993
Firstpage
116
Lastpage
119
Abstract
CMOS bridge faults have very complex behavior and make the testing difficult. This paper proposes a new technique to model all types of bridges as faulty boolean expressions. The modeling is based on analyzing the affected subcircuits using a simplified transistor model. Experiments show that this way of modeling is a good tradeoff of accuracy versus efficiency and allows fast evaluation of test patterns for large circuits.<>
Keywords
Boolean functions; CMOS integrated circuits; fault location; integrated logic circuits; logic testing; CMOS bridge fault modeling; accuracy; efficiency; faulty boolean expressions; subcircuits; test pattern evaluation; transistor model; Bridge circuits; CMOS logic circuits; CMOS technology; Circuit faults; Circuit testing; Logic design; Logic testing; SPICE; Semiconductor device modeling; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1993. Digest of Papers., Eleventh Annual 1993 IEEE
Conference_Location
Atlantic City, NJ, USA
Print_ISBN
0-8186-3830-3
Type
conf
DOI
10.1109/VTEST.1993.313297
Filename
313297
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