Title :
Classification of bridging faults in CMOS circuits: experimental results and implications for test
Author :
Midkiff, Scott F. ; Bollinger, S. Wayne
Author_Institution :
Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
Abstract :
Investigates linkages between physically realistic faults in CMOS integrated circuits and test generation and test quality. The procedure and results for an inductive fault analysis experiment that determined likely bridging faults in a set of CMOS circuits are presented. The implications of the results on test generation for physically realistic faults and on fault coverage are discussed.<>
Keywords :
CMOS integrated circuits; automatic testing; fault location; integrated logic circuits; logic testing; CMOS circuits; bridging faults; fault coverage; inductive fault analysis; physically realistic faults; test generation; test quality; Automatic testing; CMOS integrated circuits; Circuit faults; Circuit testing; Current supplies; Fault detection; Integrated circuit modeling; Integrated circuit testing; Semiconductor device modeling; Semiconductor device testing;
Conference_Titel :
VLSI Test Symposium, 1993. Digest of Papers., Eleventh Annual 1993 IEEE
Conference_Location :
Atlantic City, NJ, USA
Print_ISBN :
0-8186-3830-3
DOI :
10.1109/VTEST.1993.313298
