Classification of bridging faults in CMOS circuits: experimental results and implications for test

Author

Midkiff, Scott F. ; Bollinger, S. Wayne

Author_Institution

Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA

fYear

1993

fDate

6-8 April 1993

Firstpage

112

Lastpage

115

Abstract

Investigates linkages between physically realistic faults in CMOS integrated circuits and test generation and test quality. The procedure and results for an inductive fault analysis experiment that determined likely bridging faults in a set of CMOS circuits are presented. The implications of the results on test generation for physically realistic faults and on fault coverage are discussed.<>

Keywords

CMOS integrated circuits; automatic testing; fault location; integrated logic circuits; logic testing; CMOS circuits; bridging faults; fault coverage; inductive fault analysis; physically realistic faults; test generation; test quality; Automatic testing; CMOS integrated circuits; Circuit faults; Circuit testing; Current supplies; Fault detection; Integrated circuit modeling; Integrated circuit testing; Semiconductor device modeling; Semiconductor device testing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1993. Digest of Papers., Eleventh Annual 1993 IEEE

Conference_Location

Atlantic City, NJ, USA

Print_ISBN

0-8186-3830-3

Type

conf

DOI

10.1109/VTEST.1993.313298

Filename

313298

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1985068