• DocumentCode
    1985199
  • Title

    Explorations of sequential ATPG using Boolean satisfiability

  • Author

    Konuk, Haluk ; Larrabee, Tracy

  • Author_Institution
    California Univ., Santa Cruz, CA, USA
  • fYear
    1993
  • fDate
    6-8 April 1993
  • Firstpage
    85
  • Lastpage
    90
  • Abstract
    Presents a sequential test generation method based on Boolean satisfiability. The method produces near-minimal test sizes. The authors discuss the flexibility provided by Boolean satisfiability to extend the fault model to realistic faults. Experimental results using ISCAS-89 benchmark circuits and comparisons with previously published results are presented.<>
  • Keywords
    Boolean functions; automatic testing; integrated circuit testing; integrated logic circuits; logic testing; sequential circuits; ISCAS-89 benchmark circuits; fault model; near-minimal test sizes; sequential ATPG using Boolean satisfiability; sequential test generation method; Automatic test pattern generation; Benchmark testing; Central Processing Unit; Circuit faults; Circuit testing; Compaction; Performance evaluation; Sequential analysis; Sequential circuits; System testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium, 1993. Digest of Papers., Eleventh Annual 1993 IEEE
  • Conference_Location
    Atlantic City, NJ, USA
  • Print_ISBN
    0-8186-3830-3
  • Type

    conf

  • DOI
    10.1109/VTEST.1993.313303
  • Filename
    313303
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1985199