DocumentCode :
1985225
Title :
A hardware Gaussian noise generator for channel code evaluation
Author :
Lee, Dong-U ; Luk, Wayne ; Villasenor, John ; Cheung, Peter Y K
Author_Institution :
Dept. of Comput., Imperial Coll., London, UK
fYear :
2003
fDate :
9-11 April 2003
Firstpage :
69
Lastpage :
78
Abstract :
Hardware simulation of channel codes offers the potential of improving code evaluation speed by orders of magnitude over workstation of PC-based simulation. We describe a hardware-based Gaussian noise generator used as a key component in a hardware simulation system, for exploring channel code behavior at very low bit error rates (BERs) in the range of 10-9 to 10-10. The main novelty is the design and use of nonuniform piecewise linear approximations in computing trigonometric and logarithmic functions. The parameters of the approximation are chosen carefully to enable rapid computation of coefficients from the inputs, while still retaining extremely high fidelity to the modeled functions. The output of the noise generator accurately models a true Gaussian PDF even at very high σ values. Its properties are explored using: (a) several different statistical tests, including the chi-square test and the Kolmogorov-Smirnov test, and (b) an application for decoding of low density parity check (LDPC) codes. An implementation at 133MHz on a Xilinx Virtex-II XC2V4000-6 FPGA produces 133 million samples per second, which is 40 times faster than a 2.13GHz PC; another implementation on a Xilinx Spartan-IIE XC2S300E-7 FPGA at 62MHz is capable of a 20 times speedup. The performance can be improved by exploiting parallelism: an XC2V4000-6 FPGA with three parallel instances of the noise generator at 126 MHz can run 100 times faster than a 2.13GHz PC. We illustrate the deterioration of clock speed with the increase in the number of instances.
Keywords :
Gaussian noise; approximation theory; channel coding; field programmable gate arrays; noise generators; performance evaluation; piecewise linear techniques; random number generation; BER; Gaussian PDF; Gaussian noise; Kolmogorov-Smirnov test; LDPC; PC-based simulation; Xilinx Spartan-IIE XC2S300E-7 FPGA; Xilinx Virtex-II XC2V4000-6 FPGA; bit error rate; channel code; chi-square test; coefficient computation; computer workstation; hardware simulation system; logarithmic function; low density parity check; noise generator; piecewise linear approximation; trigonometric function; Bit error rate; Computational modeling; Field programmable gate arrays; Gaussian noise; Hardware; Noise generators; Parity check codes; Piecewise linear approximation; Testing; Workstations;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field-Programmable Custom Computing Machines, 2003. FCCM 2003. 11th Annual IEEE Symposium on
Print_ISBN :
0-7695-1979-2
Type :
conf
DOI :
10.1109/FPGA.2003.1227243
Filename :
1227243
Link To Document :
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