DocumentCode
1985298
Title
On the check base selection problem for fast adders
Author
Sparmann, U.
Author_Institution
Fachbereich Inf., Univ. des Saarlandes, Saarbrucken, Germany
fYear
1993
fDate
6-8 April 1993
Firstpage
62
Lastpage
65
Abstract
Considers the problem of selecting a suitable check base for on-line error detection by residue codes in fast adders. The dependency between structural properties of an adder and its set of possible error values is characterized. Based on this characterization an efficient procedure is developed for testing the appropriateness of a check base for a specific adder.<>
Keywords
adders; carry logic; error detection codes; check base selection problem; error values; fast adders; on-line error detection; residue codes; structural properties; Adders; Automatic testing; Circuit testing; Computer errors; Concurrent computing; Contracts; Costs; Encoding; Hardware; Virtual colonoscopy;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1993. Digest of Papers., Eleventh Annual 1993 IEEE
Conference_Location
Atlantic City, NJ, USA
Print_ISBN
0-8186-3830-3
Type
conf
DOI
10.1109/VTEST.1993.313307
Filename
313307
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