DocumentCode :
1985398
Title :
Simulation and generation of I/sub DDQ/ tests for bridging faults in combinational circuits
Author :
Chakravarty, Sreejit ; Thadikaran, Paul J.
Author_Institution :
Dept. of Comput. Sci., State Univ. of New York, Buffalo, NY, USA
fYear :
1993
fDate :
6-8 April 1993
Firstpage :
25
Lastpage :
32
Abstract :
In the absence of information about the layout and for better defect coverage test generation and fault simulation systems must target all bridging faults. The authors show that an I/sub DDQ/ Test Set that detects all two line bridging faults also detects all multiple line, single cluster bridging faults. A novel algorithm for simulating I/sub DDQ/ tests for all two-line bridging faults in combinational circuits is presented. Experimental results on using randomly generated I/sub DDQ/ test sets for detecting bridging faults are presented. These results point to the computational feasibility of targeting all two line bridging faults in combinational circuits, for the purpose of I/sub DDQ/ test generation.<>
Keywords :
CMOS integrated circuits; combinatorial circuits; fault location; integrated logic circuits; logic testing; bridging faults; combinational circuits; defect coverage test generation; fault simulation; multiple line; single cluster; test generation; two line; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Computational modeling; Computer science; Data mining; Electrical fault detection; Fault detection; System testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 1993. Digest of Papers., Eleventh Annual 1993 IEEE
Conference_Location :
Atlantic City, NJ, USA
Print_ISBN :
0-8186-3830-3
Type :
conf
DOI :
10.1109/VTEST.1993.313312
Filename :
313312
Link To Document :
بازگشت