Title :
Analysis of redundant structures in combinational circuits
Author :
Isern, E. ; Figueras, J.
Author_Institution :
Dept. d´Enginyeria Electron., Univ. Politectica de Catalunya, Barcelona, Spain
Abstract :
An efficient method for the analysis and detection of functionally equivalent nodes in combinational circuits is presented. In this work these nodes are called f-redundant nodes. The proposed method consists of two phases: First, a reduced set of pseudorandom input vectors is used to reduce the number of classes of nodes that are candidates for f-redundancy. In the second phase, ordered binary decision diagrams are used to check the equivalences between the logic functions of the remaining f-redundant node candidates. The efficiency of the proposed algorithm has been evaluated on the ISCAS´85 benchmark circuits.<>
Keywords :
combinatorial circuits; logic testing; redundancy; ISCAS´85 benchmark circuits; combinational circuits; f-redundant nodes; functionally equivalent nodes; logic functions; ordered binary decision diagrams; pseudorandom input vectors; redundant structures; Boolean functions; Bridge circuits; Circuit testing; Combinational circuits; Coupling circuits; Data structures; Logic circuits; Logic functions; Logic testing; Sun;
Conference_Titel :
VLSI Test Symposium, 1993. Digest of Papers., Eleventh Annual 1993 IEEE
Conference_Location :
Atlantic City, NJ, USA
Print_ISBN :
0-8186-3830-3
DOI :
10.1109/VTEST.1993.313313
