• DocumentCode
    1985417
  • Title

    Radiation Environment Emulation for VLSI Designs: A Low Cost Platform based on Xilinx FPGA´s

  • Author

    Nápoles, J. ; Guzman, Hugo ; Aguirre, M. ; Tombs, J.N. ; Munoz, Felipe ; Baena, V. ; Torralba, A. ; Franquelo, L.G.

  • Author_Institution
    Univ. de Sevilla, Sevilla
  • fYear
    2007
  • fDate
    4-7 June 2007
  • Firstpage
    3334
  • Lastpage
    3338
  • Abstract
    As technology shrinks, critical industrial applications have to be designed with special care. VLSI circuits become more sensitive to ambient radiation: it affects to the internal structures, combinational or sequential elements. The effects, known as single event effects (SEEs), are modeled as spontaneous logical changes in a running netlist. They can be mitigated at netlist design level by means of inserting massive redundancy logic in the IC memory elements, as well as designing robust deadlock-free state machines. Current techniques for the analysis and verification of the protection logic for VLSI are inefficient and expensive, lacking either speed or analysis. This paper presents the FT- As technology shrinks, critical industrial applications have to be designed with special care. VLSI circuits become more sensitive to ambient radiation: it affects to the internal structures, combinational or sequential elements. The effects, known as single event effects (SEEs), are modeled as spontaneous logical changes in a running netlist. They can be mitigated at netlist design level by means of inserting massive redundancy logic in the IC memory elements, as well as designing robust deadlock-free state machines. Current techniques for the analysis and verification of the protection logic for VLSI are inefficient and expensive, lacking either speed or analysis. This paper presents the FT-UNSHADES system. This system is a low cost emulator focused on bit-flip insertion and SEE analysis at hardware speed, based on a Xilinx Virtex-II. Radiation tests are emulated in a highly controlled process, using a non-intrusive method. As a result the system can insert and analyse at least 80 K faults per hour in a system with 2 million test vectors.UNSHADES system. This system is a low cost emulator focused on bit-flip insertion and SEE analysis at hardware speed, based on a Xilinx Virtex-II. Radiation tests are emulated in a highly controlled process, using a non-intrusive method. As - a result the system can insert and analyse at least 80 K faults per hour in a system with 2 million test vectors.
  • Keywords
    VLSI; circuit reliability; fault tolerance; field programmable gate arrays; integrated circuit design; logic CAD; radiation; redundancy; FT-UNSHADES system; IC memory elements; VLSI designs; Xilinx FPGA; Xilinx Virtex-II; bit-flip insertion; deadlock-free state machines design; fault tolerance; netlist design; radiation environment emulation; redundancy logic; single event effects; Circuits; Costs; Emulation; Field programmable gate arrays; Logic design; Protection; Redundancy; Robustness; System recovery; Very large scale integration; FPGA; Fault Tolerant; Partial Reconfiguration; Radiation; Reliability; VLSI design;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Industrial Electronics, 2007. ISIE 2007. IEEE International Symposium on
  • Conference_Location
    Vigo
  • Print_ISBN
    978-1-4244-0754-5
  • Electronic_ISBN
    978-1-4244-0755-2
  • Type

    conf

  • DOI
    10.1109/ISIE.2007.4375150
  • Filename
    4375150