A 0.24-/spl mu/m/sup 2/ cell process with 0.18-/spl mu/m width isolation and 3-D interpoly dielectric films for 1-Gb flash memories

Author

Kobayashi, T. ; Mastsuzaki, N. ; Sato, A. ; Katayama, A. ; Kurata, H. ; Miura, A. ; Mine, T. ; Goto, Y. ; Morimoto, T. ; Kume, H. ; Kure, T. ; Kimura, K.

Author_Institution

Central Res. Lab., Hitachi Ltd., Kokubunji, Japan

fYear

1997

fDate

10-10 Dec. 1997

Firstpage

275

Lastpage

278

Abstract

We have developed a 0.24-/spl mu/m/sup 2/ contactless-array flash memory cell by using 0.2-/spl mu/m process technology. For reducing the data line pitch, a 0.18-/spl mu/m-wide self-aligned shallow groove isolation (SGI) is formed between memory cells, by filling the grooves with boron phosphosilicate glass (BPSG), to maintain the isolation breakdown voltage. In addition, three-dimensional (3-D) CVD SiO/sub 2/ single-layer interpoly dielectric films with high capacitance are employed to decrease the internal operating voltage by increasing the coupling ratio. These processes are the keys to fabricating 1-Gb flash memory cells.

Keywords

CVD coatings; EPROM; dielectric thin films; integrated memory circuits; isolation technology; silicon compounds; 0.18 micron; 1 Gbit; B2O3-P2O5-SiO2; BPSG; SiO/sub 2/; boron phosphosilicate glass; breakdown voltage; capacitance; contactless-array flash memory cell fabrication; coupling ratio; data line pitch; internal operating voltage; process technology; self-aligned shallow groove isolation; three-dimensional CVD SiO/sub 2/ single-layer interpoly dielectric film; Boron; Capacitance; Dielectric films; Dry etching; Filling; Flash memory; Flash memory cells; Nonvolatile memory; Voltage; Wet etching;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-4100-7

Type

conf

DOI

10.1109/IEDM.1997.650380

Filename

650380