Design of the analog components for a high sampling rate continuous time ΣΔ modulator in 0.4 μm HEMT technology

The design of the key components for a high sampling rate ΣΔ modulator implemented on a 0.4 μm InGaP-InGaAs HEMT technology is described. The circuit, a 2nd-order continuous-time ΣΔ modulator, has a fully differential architecture including pairs of highly linear V-I converters, high-speed opamps, high-speed 1-bit DAC units, and a new polarity alternating feedback (PAF) comparator. Working at a sampling rate of 4.9 GHz and a signal bandwidth of 100 MHz, the fabricated modulator exhibits 43 dB signal-to-noise ratio (SNR), equivalent to 7.2 bits resolution. The circuit occupies an active area of 0.9 mm², and dissipates 400 mW from a 3.2 V power supply. Such performance corresponds to the highest sampling rate and lowest power consumption for an oversampled A/D converter in III-V technology known to us