Multimedia processor architecture

The paper describes trends in the development of multimedia processor architecture that may be predicted on the basis of the availability of an ASIC with 10s of millions of gates. Multimedia processing based upon multi granular parallelism for diverse media needs supercomputing power for multi threaded, process level execution. Due to the appearance of large scale integration (LSI) for what has been termed system on silicon, a new scheme for building the multimedia centric processor will be realized. The paper proposes advanced implementation technologies for multimedia acceleration employing a reconfigurable architecture and using hundreds of processing elements embedded within an ASIC. Accelerated functions considered in this proposal include 3D graphic and 3D audio rendering, and implementation of video and audio codecs. Computational efficiency for advanced applications, such as walk through virtual reality (VR), is maximized by sharing the results of geometric calculations that are required both for graphics and audio rendering