Title :
Worst-case analysis for pseudorandom testing
Author :
Marculescu, Radu
Author_Institution :
Dept. of Comput. Sci., Polytech. Inst. of Bucharest, Romania
Abstract :
The testing problem of combinational circuits with pseudorandom patterns is investigated. Work by previous workers for single faults is extended to multiple faults situations; in addition, masking effects between disjoint/conjoint faults are considered. An analytical model based on Markov chains with any number of states is proposed for random/pseudorandom testing and relationships between test length and test confidence are developed. Evaluations of the model for double and triple faults are presented using well-known examples. The results presented in this paper are useful for BIST systems that use random/pseudorandom input patterns.<>
Keywords :
built-in self test; combinatorial circuits; fault location; logic testing; BIST systems; combinational circuits; disjoint/conjoint faults; double faults; masking effects; multiple faults situations; pseudorandom patterns; pseudorandom testing; test confidence; test length; triple faults; Built-in self-test; Circuit faults; Circuit testing; Combinational circuits; Computer science; Electrical fault detection; Fault detection; Predictive models; System testing; Very large scale integration;
Conference_Titel :
VLSI Test Symposium, 1993. Digest of Papers., Eleventh Annual 1993 IEEE
Conference_Location :
Atlantic City, NJ, USA
Print_ISBN :
0-8186-3830-3
DOI :
10.1109/VTEST.1993.313325
