Comparator-based switched-capacitor pipelined ADC with background offset calibration

A background offset calibration technique for a comparator-based switched-capacitor (CBSC) circuit is proposed. The calibration circuitry employs a dynamic latch to determine an offset and an auxiliary differential input pair to cancel the offset. Since the proposed technique does not require additional auto-zeroing or offset detecting periods, it is suitable for high-speed low-power operations. A prototype 10-bit 100- MS/s pipelined CBSC ADC is designed and simulated in a 0.13μm CMOS process. Post-layout simulation results show the prototype ADC achieves 9.5 ENOB with a 25.4-MHz sinusoidal input signal and power consumption is 5.9 mW.