Title :
Degrading fault model for WSI interconnection lines
Author :
Abujbara, H.Y. ; Al-Arian, S.A.
Author_Institution :
Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
Abstract :
A new fault model is proposed which accounts for both degrading and catastrophic fault types, which exist in WSI/VLSI designs. Fault degrading is the result of a defect mechanism which has no effect on the logical behavior of the circuit, but rather causes performance degradation to the circuit. This degradation is manifested in poor signal propagation delays, and weak noise immunity. However, there are no testing techniques and no fault models that are capable of handling the testing of the degrading fault by using digital fault simulation. A defect model that is capable of mapping degrading defects syndrome into a Boolean behavior (syndrome) would make it possible to use higher speed digital fault simulation techniques, rather than analog parametric testing. This approach for testing is more reliable and would cover both degrading and fatal (catastrophic) faults in the system.<>
Keywords :
VLSI; digital simulation; fault location; metallisation; Boolean behavior; WSI interconnection lines; WSI/VLSI designs; catastrophic fault types; defect mechanism; degrading fault; digital fault simulation techniques; fault model; performance degradation; signal propagation delays; weak noise immunity; Boolean functions; Bridge circuits; Circuit faults; Circuit noise; Circuit testing; Degradation; Driver circuits; Integrated circuit interconnections; Logic circuits; Propagation delay;
Conference_Titel :
VLSI Test Symposium, 1993. Digest of Papers., Eleventh Annual 1993 IEEE
Conference_Location :
Atlantic City, NJ, USA
Print_ISBN :
0-8186-3830-3
DOI :
10.1109/VTEST.1993.313326
