Fast reconfiguration through difference compression

Advances in the configurable logic fabric´s architecture, together with the increasing hard-wired integration of commonly used cores such as giga-bit I/O transceivers, multipliers and processors suggests that statically configured FPGA (field programmable gate array) platforms will continue to become more competitive and therefore gain further market share at the expense of the ASIC. In addition, the Semiconductor Association predicts that the percentage area of memory in a system-on-chip (SOC) will continue to increase, with 70% of a SOC are devoted to RAM by 2005. However, it is not certain whether it is valid to combine these observations and extrapolations to predict the demise of the ASIC as some FPGA vendors believe. One of the main arguments made against this prediction is the size of the silicon are gap between an ASIC solution and an FPGA solution is largely attributed to the area inefficiency of the FPGA configurable logic fabric. Dynamic partial reconfiguration can help significantly reduce this are inefficiency gap.