Title :
Design SRAMs for burn-in
Author :
Reohr, W. ; Yuen Chan ; Plass, D. ; Pelella, A. ; Wu, P.
Author_Institution :
IBM East Fishkill Facility, Hopewell Junction, NY, USA
Abstract :
SRAM designers and product engineers must balance the diverse aspects involved in developing and manufacturing quality ICs. This paper describes how cost and complexity design techniques to improve burn-in, noting implications for performance, power and density.<>
Keywords :
SRAM chips; circuit reliability; SRAMs; burn-in; complexity design techniques; density; performance; power; quality ICs; Aging; Built-in self-test; Chip scale packaging; Circuit testing; Compressors; Conductors; Costs; Heating; Ovens; Random access memory;
Conference_Titel :
VLSI Test Symposium, 1993. Digest of Papers., Eleventh Annual 1993 IEEE
Conference_Location :
Atlantic City, NJ, USA
Print_ISBN :
0-8186-3830-3
DOI :
10.1109/VTEST.1993.313330
