A pipelined SoPC architecture for 2.5 Gbps network processing

This paper presents the architecture and implementation of a 2.5 Gbps Programmable Point-to-Point-Protocol Processor (P5) on a Virtex II FPGA (field programmable gate array). A 32-bit wide pipelined processor circuit is implemented for layer 2 frame processing and a Leon processor core is embedded for higher layer PPP (point-to-point protocol) control protocol processing. An AMBA bus interface is used to interlink the Leon processor to the hardware frame processing unit and presents a standard interface allowing easy retargeting to other processor platforms. Complex memory control is implemented to enable the microprocessor to handle the extreme data rate. The high-level system breakdown is described and Virtex II synthesis results are presented.