• DocumentCode
    1985793
  • Title

    Defect-tolerant cache memory design

  • Author

    Lamet, Dan ; Frenzel, James F.

  • Author_Institution
    Dept. of Electr. Eng., Idaho Univ., Moscow, ID, USA
  • fYear
    1993
  • fDate
    6-8 April 1993
  • Firstpage
    159
  • Lastpage
    163
  • Abstract
    The design of a defect-tolerant control circuit for a set-associative cache memory is presented. The circuit maintains the stack ordering necessary for implementing the LRU replacement algorithm. A discussion of programming techniques for bypassing defective blocks is included.<>
  • Keywords
    buffer storage; storage management chips; LRU replacement algorithm; defect-tolerant control circuit; defective blocks; programming techniques; set-associative cache memory; stack ordering; Added delay; Cache memory; Cache storage; Circuit testing; Costs; Geometry; Hardware; NASA; Pulp manufacturing; Redundancy;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium, 1993. Digest of Papers., Eleventh Annual 1993 IEEE
  • Conference_Location
    Atlantic City, NJ, USA
  • Print_ISBN
    0-8186-3830-3
  • Type

    conf

  • DOI
    10.1109/VTEST.1993.313331
  • Filename
    313331
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1985793