Title :
Revisiting shift register realization for ease of test generation and testing
Author_Institution :
Dept. of Comput. Sci., Old Dominion Univ., Norfolk, VA, USA
Abstract :
The shift register realization of sequential circuits is reexamined. Though the shift register realization requires no extra circuits for scan, and shortens test application time, it in general requires many memory elements. This paper presents a method to reduce the number of memory elements in a shift register realization.<>
Keywords :
logic testing; sequential circuits; shift registers; memory elements; sequential circuits; shift register realization; test application time; test generation; Application software; Circuit faults; Circuit testing; Computer science; Feedback loop; Flip-flops; Redundancy; Sequential analysis; Sequential circuits; Shift registers;
Conference_Titel :
VLSI Test Symposium, 1993. Digest of Papers., Eleventh Annual 1993 IEEE
Conference_Location :
Atlantic City, NJ, USA
Print_ISBN :
0-8186-3830-3
DOI :
10.1109/VTEST.1993.313333
