Generation of testable designs from behavioral descriptions using high level synthesis tools

Develops a synthesis-for-testability procedure wherein behavioral modeling techniques are used to generate testable designs. Knowledge about the accessibility of embedded modules is extracted from the behavioral design, analyzed, and any modification required subsequently incorporated in the behavioral design. Results show that when the resulting testable circuit is synthesized from this modified design using a high level synthesis tool, the overhead for testability is quite small, especially for large circuits.<>