A triple polysilicon stacked flash memory cell with wordline self-boosting programming

A novel triple polysilicon stacked flash cell by the wordline boosting is proposed as a solution for a low voltage operation. The third gate named as booster gate is simply stacked and self-aligned on the conventional control gate. The successively coupled booster gate bias in addition to the precharged control gate voltage is a key to increase the floating gate potential. A new NAND flash cell array with 0.51 /spl mu//sup 2/ cell size is fabricated using the 0.32 /spl mu/m process technology. A triple stacked polysilicon structure is patterned with a single self-alignment etching technology. With the booster gate bias, significantly enhanced coupling to the floating gate is obtained through the self-boosted control gate voltage. Thus, for the first time, a 11 V programming voltage is achieved at 300 /spl mu/s programming time in the multi-bit NAND flash cell.