Title :
Incremental test pattern generation
Author :
Song, Sang-Hoon ; Kinney, Larry L.
Author_Institution :
Dept. of Comput. Sci., Se-Jong Univ., Seoul, South Korea
Abstract :
Discusses a test pattern generation (TPG) algorithm for single stuck-at faults in combinational logic circuits. Current TPG systems generate a test vector for fault F/sub i+1/ independently of the computation previously done for faults F/sub 1/, F/sub 2/, . . ., F/sub i/. The algorithm ITPG, generates a test vector for fault F/sub i+1/ by starting with (inheriting) the test vector for fault F/sub i/. A new test vector is generated from inherited values by gradually changing the inherited values. The inherited values may partially activate a fault and propagate the fault signal. Normally, this reduces the number of decision steps and backtracks in the second search. Experimental results for well-known benchmark circuits show that ITPG is very efficient with a small backtrack limit; in combination with other algorithms, it is very efficient for arbitrary backtrack limits.<>
Keywords :
automatic testing; combinatorial circuits; fault location; logic testing; ITPG; backtracks; benchmark circuits; combinational logic circuits; decision steps; inherited values; single stuck-at faults; test pattern generation; test vector; Benchmark testing; Circuit faults; Circuit testing; Combinational circuits; Computer science; Logic testing; Pulse inverters; System testing; Terminology; Test pattern generators;
Conference_Titel :
VLSI Test Symposium, 1993. Digest of Papers., Eleventh Annual 1993 IEEE
Conference_Location :
Atlantic City, NJ, USA
Print_ISBN :
0-8186-3830-3
DOI :
10.1109/VTEST.1993.313353
