Title :
Time and space correlated errors in signature analysis
Author :
Edirisooriya, G. ; Edirisooriya, S. ; Robinson, J.P.
Author_Institution :
Motorola Comput. Group, Tempe, AZ, USA
Abstract :
A new error model that considers both space and time correlation is proposed. An exact closed form expression for aliasing probability is obtained for an arbitrary test length for a large class of signature registers. The authors identify the minimum register structure that falls into this class.<>
Keywords :
VLSI; built-in self test; integrated logic circuits; logic testing; probability; shift registers; aliasing probability; arbitrary test length; closed form expression; error model; minimum register structure; signature analysis; space correlated errors; time correlation; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Computer errors; Electrical fault detection; Error analysis; Fault detection; Registers; Very large scale integration;
Conference_Titel :
VLSI Test Symposium, 1993. Digest of Papers., Eleventh Annual 1993 IEEE
Conference_Location :
Atlantic City, NJ, USA
Print_ISBN :
0-8186-3830-3
DOI :
10.1109/VTEST.1993.313357
