DocumentCode
1986037
Title
Aliasing computation using fault simulation with fault dropping
Author
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
fYear
1993
fDate
6-8 April 1993
Firstpage
282
Lastpage
288
Abstract
Accurate analysis of aliasing in built-in test environments is considered highly computation intensive, due to the requirement to perform nonfault dropping fault simulation. Fault dropping is possible when computing the exact aliasing of modeled faults for common output response compression circuits. Fault dropping is most effective when the test set size is small. Extensions to large test sets are also considered. The authors present a fault simulation procedure that takes advantage of fault dropping and present experimental results to support its effectiveness.<>
Keywords
built-in self test; fault location; logic testing; shift registers; aliasing; built-in test environments; fault dropping; fault simulation; nonfault dropping fault simulation; output response compression circuits; test set size; Analytical models; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; Cities and towns; Computational modeling; Hardware; High performance computing; Linear feedback shift registers;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1993. Digest of Papers., Eleventh Annual 1993 IEEE
Conference_Location
Atlantic City, NJ, USA
Print_ISBN
0-8186-3830-3
Type
conf
DOI
10.1109/VTEST.1993.313358
Filename
313358
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