• DocumentCode
    1986072
  • Title

    Physical design for testability for bridges in CMOS circuits

  • Author

    Ferguson, F.J.

  • Author_Institution
    Board of Studies in Comput. Eng., California Univ., Santa Cruz, CA, USA
  • fYear
    1993
  • fDate
    6-8 April 1993
  • Firstpage
    290
  • Lastpage
    295
  • Abstract
    Present research in design for testability has largely been confined to the logic level. This paper presents directions for research in design for testability at the layout or physical design level. These are illustrated for bridge faults in circuits consisting of CMOS standard cells.<>
  • Keywords
    CMOS integrated circuits; cellular arrays; circuit layout CAD; design for testability; integrated logic circuits; logic CAD; CMOS circuits; bridges; design for testability; layout; physical design level; standard cells; testability; Bridge circuits; CMOS logic circuits; Circuit faults; Circuit testing; Delay; Design for testability; Logic design; Logic testing; System testing; Test pattern generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium, 1993. Digest of Papers., Eleventh Annual 1993 IEEE
  • Conference_Location
    Atlantic City, NJ, USA
  • Print_ISBN
    0-8186-3830-3
  • Type

    conf

  • DOI
    10.1109/VTEST.1993.313361
  • Filename
    313361
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1986072