Verilog implementation of genetic algorithm for minimum leakage vector in input vector control approach

Leakage power dissipation plays a major role in the total power dissipation with the advancement in the technology. Reduction of leakage power is of top concern in the present trend of nanotechnology. Input Vector Control (IVC) is one of the approaches used for static power reduction during standby mode. Leakage in a circuit depends on input vector applied at primary inputs due to stacking effect. Minimum leakage vector (MLV) is the input vector to which a circuit can offer a minimum leakage for a given set of test inputs. This paper presents MLV for various test circuits using genetic algorithm. The algorithm is implemented in Verilog HDL to obtain MLV. Results explores that heuristic approaches can be considered as better algorithms in finding optimum solution. Another advantage found during simulation is that implementation of algorithm in HDL converges in less number of iterations with runtime savings compared to random search method.