Title :
A dual-loop delay locked loop with multi digital delay lines for GHz DRAMs
Author :
Moon, Jinyeong ; Lee, Hye-young
Author_Institution :
DRAM Design Team II, Hynix Semicond. Inc., Icheon, South Korea
Abstract :
In this paper, a new low-jitter dual-loop delay locked loop (DLL) with multi digitally controlled delay lines (DCDLs) is proposed. With this proposal, a limitation on unit delay amount is drastically reduced; hence the maximum frequency that a dual-loop DLL supports can be easily expanded into GHz range. Also, the invalidation system employed in the reference delay loop helps reduce the jitter in the final output clock of the DLL.
Keywords :
DRAM chips; clocks; delay lines; delay lock loops; jitter; DRAM; clock; dual-loop delay locked loop; low-jitter; multidigitally controlled delay lines; reference delay loop; Clocks; Delay; Delay lines; Detectors; Jitter; Noise; Random access memory;
Conference_Titel :
Circuits and Systems (ISCAS), 2011 IEEE International Symposium on
Conference_Location :
Rio de Janeiro
Print_ISBN :
978-1-4244-9473-6
Electronic_ISBN :
0271-4302
DOI :
10.1109/ISCAS.2011.5937564
