Complex-multiplier implementation for pipelined FFTs in FPGAs

Different approaches for implementing a complex multiplier in pipelined FFT are considered and implemented to find an efficient one in this paper. The design is implemented in VHDL and design is synthesized on FPGA to know the performance. The design is implemented with a focus of reducing the resources used. Some approaches resulted in the reduced number of DSP blocks and others resulted in reduced number of LUTs. Analysis of Synthesis results is performed for different widths (bit lengths) of complex multiplier approaches.