Title :
On diagnosis of faults in a scan-chain
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
Testing screens for good chips. However, when test fall out is high (low yield) it becomes necessary to diagnose faults so that the manufacturing process or physical design can be fixed to improve yield. Several scan based diagnostic schemes are used in industry. They work when the scan chain itself is fault free. This paper describes a diagnosis system that can diagnose faults in a scan chain.<>
Keywords :
boundary scan testing; fault location; logic testing; production testing; diagnosis system; manufacturing process; physical design; scan based diagnostic schemes; scan-chain; test fall out; yield; Circuit faults; Clocks; Fault diagnosis; Flip-flops; Latches; Manufacturing industries; Manufacturing processes; Microscopy; Process design; Testing;
Conference_Titel :
VLSI Test Symposium, 1993. Digest of Papers., Eleventh Annual 1993 IEEE
Conference_Location :
Atlantic City, NJ, USA
Print_ISBN :
0-8186-3830-3
DOI :
10.1109/VTEST.1993.313363
