Title :
Partial scan testing with single clock control
Author :
Agrawal, Vishwani D. ; Charkraborty, T.J.
Author_Institution :
AT&T Bell Labs., Murray Hill, NJ, USA
Abstract :
Gives methods of test generation for partial scan circuits in which a single system clock controls all flip-flops in both functional and scan modes. Scan flip-flops are selected to break cycles. In comparison to circuits with separate scan clock, the single clock tests can cover most detectable faults with shorter test sequence. However, test generation time is increased.<>
Keywords :
automatic testing; boundary scan testing; clocks; fault location; flip-flops; logic testing; detectable faults; flip-flops; functional modes; partial scan circuits; scan modes; single clock control; test generation; test generation time; test sequence; Circuit faults; Circuit testing; Clocks; Controllability; Electrical fault detection; Fault detection; Flip-flops; Sequential analysis; Sequential circuits; System testing;
Conference_Titel :
VLSI Test Symposium, 1993. Digest of Papers., Eleventh Annual 1993 IEEE
Conference_Location :
Atlantic City, NJ, USA
Print_ISBN :
0-8186-3830-3
DOI :
10.1109/VTEST.1993.313365
