Variation-resilient CNFET-based 8T SRAM cell for ultra-low-power application

Local and global process fluctuations causes increase in threshold voltage (V,) variation in ultra-short channel devices like CMOS. Therefore, it is not possible to operate the CMOS based 6-Transistor (6T) SRAM cell bellow 600 mV. Hence, to mitigate the effect of process fluctuations a CNFET based 8T SRAM cell is proposed in this article. Different design metrics of an SRAM cell are accessed for the proposed cell and to show its effectiveness, the design metrics are compared with its conventional counterpart. The proposed cell consumes 2.06× less power during hold mode and it also offers improvement in write delay (read delay) by 5.23× (4.41×) @ 200 mV compared to conventional CMOS based 8T cell. It depicts its robustness against process fluctuations by showing narrower spread in write delay (95.17%), read delay (75.20%) and hold power consumption (87.34%) for the same supply voltage. The proposed CNFET based 8T cell shows 59.41% higher read stability @ 400 mV than the CMOS based 8T SRAM cell.