Title :
Functional verification and simulation of FSM networks
Author :
Hasan, Zafar ; Ciesielski, Maciej J.
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Abstract :
Presents a method to functionally verify a network of interacting finite state machines (FSMs) at any level of abstraction. The verification tool developed can verify the FSM network at various stages of the synthesis process. It can verify the result of FSM decomposition both in the symbolic and binary-coded form. The tool has various options to help the designer in the synthesis of a decomposed sequential machine system. It can generate the decomposed submachines for a given decomposition from the prototype specification. It can also be used to simulate the network. An efficient enumeration-simulation method is used to traverse the state transition graph of the prototype machine in a depth first fashion. The algorithm can be used to verify the decomposed system even if the decomposition information is not known, thus allowing it to verify any FSM network.<>
Keywords :
VLSI; finite state machines; logic CAD; sequential machines; FSM decomposition; FSM networks; binary-coded form; decomposed sequential machine system; enumeration-simulation method; finite state machines; functional verification; state transition graph; symbolic form; synthesis process; verification tool; Automata; Circuits; Computational modeling; Computer networks; Diodes; Encoding; Logic; Network synthesis; Prototypes; Very large scale integration;
Conference_Titel :
VLSI Test Symposium, 1993. Digest of Papers., Eleventh Annual 1993 IEEE
Conference_Location :
Atlantic City, NJ, USA
Print_ISBN :
0-8186-3830-3
DOI :
10.1109/VTEST.1993.313371
