Modeling of Low-Frequency Noise in Junction Field-Effect Transistor with Self-Aligned Planer Technology

The noise behaviors of the junction field-effect transistor (JFET) fabricated with self-aligned planer technology are studied. The device structure being considered has a wide separation between source-gate and drain-gate with a shallow trench isolation (STI) technique. High noise level is found in the devices with STI and the normalized drain noise is found to be gate bias dependent. The excess noise is identified as the surface noise generated in the STI regions and a model is developed to explain the bias dependence of the noise characteristics. To reduce the noise level, the STI region should be kept small and better oxidation technique should be employed for the STI passivation.