Title :
A model for testing reliable VLSI routing architectures
Author_Institution :
Dept. of Comput. Sci., Fairleigh Dickinson Univ., Madison, NJ, USA
Abstract :
Presents a model for testing the reliability of VLSI interconnection topologies. It is assumed that terminals on an electronic board may fail to operate independently and with manufacturer-supplied probabilities. The authors are concerned with the ability of the operating terminals to communicate in order to carry out their tasks. The two schemes examined are the channel and match-box routing topologies which are translated to their underlying probabilistic graphs as an illustration of the applicability of combinatorial optimization techniques. Their optimality is tested under all possible failure vectors.<>
Keywords :
VLSI; circuit layout; circuit reliability; graph theory; network topology; channel routing; combinatorial optimization; failure vectors; manufacturer-supplied probabilities; match-box routing topologies; operating terminals; probabilistic graphs; reliability; reliable VLSI routing architectures; Circuit topology; Computer architecture; Computer science; Design optimization; Electronic equipment; Manufacturing; Routing; Testing; Very large scale integration; Wires;
Conference_Titel :
VLSI Test Symposium, 1993. Digest of Papers., Eleventh Annual 1993 IEEE
Conference_Location :
Atlantic City, NJ, USA
Print_ISBN :
0-8186-3830-3
DOI :
10.1109/VTEST.1993.313373
