Sensitivity analysis of a radiation immune CMOS logic family under defect conditions

Author

Ingermann, E.H. ; Frenzel, J.F.

Author_Institution

Dept. of Electr. Eng., Idaho Univ., Moscow, ID, USA

fYear

1993

fDate

6-8 April 1993

Firstpage

355

Lastpage

357

Abstract

Simulation of resistive shorts is performed on a recently developed single event upset immune logic family. Critical resistances and resultant transition delay times are compared with those of traditional CMOS logic. Behavior of the logic under these simulated defects is discussed.<>

Keywords

CMOS integrated circuits; integrated logic circuits; radiation hardening (electronics); sensitivity analysis; defect conditions; radiation immune CMOS logic family; resistive shorts; sensitivity analysis; single event upset; transition delay; CMOS logic circuits; CMOS process; CMOS technology; Circuit faults; Delay; Semiconductor device modeling; Sensitivity analysis; Space technology; Virtual manufacturing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1993. Digest of Papers., Eleventh Annual 1993 IEEE

Conference_Location

Atlantic City, NJ, USA

Print_ISBN

0-8186-3830-3

Type

conf

DOI

10.1109/VTEST.1993.313378

Filename

313378

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1986313