Title :
A 5.4 Gb/s clock and data recovery circuit using the seamless loop transition scheme without phase noise degradation
Author :
Lee, Won-Young ; Kim, Lee-Sup
Author_Institution :
Dept. of Electr. Engeering, KAIST, Daejeon, South Korea
Abstract :
This paper presents a 5.4 Gb/s clock and data recovery circuit using the seamless loop transition scheme which has no phase noise degradation. The controllable loop filter enables the CDR circuit to change the operation mode without the output phase noise degradation and the stability problem. The modified half-rate linear phase detector reduces the phase error between the data and clock. A tested chip is manufactured using 0.13 μm CMOS technology. The RMS jitter of the proposed CDR circuit is 5.98 ps-rms, which is 2.61 ps lower than the CDR circuit with the conventional scheme. The measured power dissipation is 138 mW with off-chip drivers at 5.4 Gb/s data rate.
Keywords :
CMOS integrated circuits; clock and data recovery circuits; filters; integrated circuit manufacture; integrated circuit testing; jitter; phase detectors; phase noise; CDR circuit; CMOS technology; RMS jitter; bit rate 5.4 Gbit/s; clock and data recovery circuit; controllable loop filter; modified half-rate linear phase detector; output phase noise degradation; power 138 mW; seamless loop transition scheme; size 0.13 mum; tested chip manufacturing; time 2.61 ps; Bandwidth; Charge pumps; Circuit stability; Clocks; Detectors; Phase noise;
Conference_Titel :
Circuits and Systems (ISCAS), 2011 IEEE International Symposium on
Conference_Location :
Rio de Janeiro
Print_ISBN :
978-1-4244-9473-6
Electronic_ISBN :
0271-4302
DOI :
10.1109/ISCAS.2011.5937594